1. Field of the Invention
The present invention relates to general purpose digital data processing systems, and more particularly, to such systems that employ one or more storage controllers shared amongst multiple instruction processors and input/output processors in a multi-processor system.
2. Description of the Prior Art
In most general purpose digital computers, it is desirable to have a computer system which may efficiently operate with multiple instruction processors and input/output processors in a multi-processing environment. In particular, it is desirable that storage controllers be used which may be shared amongst multiple instruction processors and input/output processors in symmetrical multi-processor systems. It is therefore desirable to have a storage controller which uses an interconnect scheme that scales in system performance as the number of common storage controllers are increased.
One approach to solve this problem uses storage controllers connected to a bi-directional system bus. The system may have four storage controllers, with each storage controller containing a dedicated second level cache, an input/output processor, and four main storage units. The instruction processors may be connected to the storage controllers via separate address and data lines. With this approach, the system bus interconnects all of the storage controllers, I/O processors, and memory storage units together in a coherent symmetrical multi-processing system. This approach has the advantage of being a very cost-effective method of interconnecting the multi-processor computing system. To improve system performance, more storage controller and instruction processor modules may be added. Memory storage unit modules may be added to increase the size of memory available to the system. In addition, I/O modules may be added to a back plane that contains the system bus interconnection. Unfortunately, a significant disadvantage with this approach is that the system bus may become overloaded with activity for applications that share a lot of data, such as transaction environments. In addition, system performance may not scale linearly as additional components are added. Therefore, this type of system is best suited for low cost and low performance applications.
Another approach which has been used to solve this problem is to directly employ the storage controller as the interconnect amongst various system modules. With this approach, all instruction processors and I/O may access directly each second level cache segment, and each second level cache segment is mapped to one of the memory storage units. This approach has better performance characteristics in transaction environments than the previous approach because the shared data is directly and readily accessible to all instruction processors and I/O via the storage controller. In addition, because the system interconnect is based on logical interconnection within the storage controller, rather than on the back plane interconnection of the previous approach, there is significantly more parallelism available with this approach. Unfortunately, this type of system interconnect which is based on logical interconnection within the storage controller has higher cost due to the relatively more complex design of the storage controller. In addition, this type of interconnect lacks component scalability, thus potentially limiting maximum performance. Furthermore, lower performance systems, such as those with one or two instruction processors, have the full cost burden of the maximum size storage controller utilizing up to four instruction processors. Unfortunately, this type of interconnection scheme is not cost-effective for systems requiring only low levels of performance. For example, in a 1.times. system, the storage controller would have to maintain the overhead cost of three unused instruction processor/storage controller interfaces. In addition, this approach would have excessive second level cache capacity that while being used, would not be as cost and performance effective as it would have been if used in a larger processing system.